1. Field of the Invention
The present invention relates to an integrated circuit including GaAs FETs (Field Effect Transistors), more particularly to an interface circuit in a DCFL (Direct Coupled FET Logic) circuit.
2. Description of the Related Art
Of late, the high responsiveness and low power consumption of logic circuits employing GaAs-MESFETs have received the attention of practitioners and been gradually developed. However, as is well known in the art, a logic circuit employing GaAs-MESFETs is inferior, in terms of a capacity for driving a load circuit, to a logic circuit such as an ECL (Emitter Coupled Logic) circuit employing silicon bipolar elements. Taking this into consideration, a buffer circuit is additionally used to improve the capacity for driving a load circuit when the input capacitance of the load circuit is low.
For example, in a conventional integrated circuit employing a DCFL circuit, a push-pull buffer circuit 20 which includes GaAs-MESFETs Q3 and Q4 is connected to an inverter 10 including GaAs-MESFETs Q1 and Q2, as shown in FIG. 1. In this drawing, GaAs-MESFETs Q5 and Q6 form a part of an inverter 30 which serves as the input section of another integrated circuit.
In the conventional integrated circuit shown in FIG. 1, the FETs Q2 and Q4 are turned off when an input signal VIN, which is supplied to the gate of the FET Q2, changes to a low level. As a result of the turning off of the FETs Q2 and Q4, the voltage applied to the gate of the FET Q3 through the FET Q1 rises almost to the level of a power source potential VDD, turning the FET Q3 on, such that an output signal VOUT changes to a high level. Then, the level of this signal VOUT falls to the Schottky potential (0.6 to 0.7 V) of the FET Q5 included in the inverter 30 serving as the input section of another integrated circuit. In this condition, the voltage VGS between the gate and source of the FET Q3 is high enough to produce a large amount of drain current ID which flows into the FET Q3. This current ID is expressed by the following equation 1: EQU ID=K(VGS-VTH).sup.2 1)
(where K is a constant, and VTH is the threshold voltage of the FET Q3.)
The drain current ID passing through the FET Q3 flows to the source of the FET Q5 via the gate and Schottky junction thereof. Due to such a drain current, low power consumption, which is one of the features of a logic circuit employing GaAs-MESFETs, is lost.